Verilog: modport port expressions - #1985
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Implements IEEE 1800-2017 25.5.2 modport port expressions, which allow naming sub-expressions of interface signals in a modport declaration: modport split(input .upper_half(data[7:4]), input .lower_half(data[3:0])); The parser is extended to accept the `direction . name ( expr )` syntax. During interface port instantiation, the modport port expressions are type-checked and added to the symbol table so that hierarchical access (e.g., port.upper_half) resolves to the underlying expression.
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Summary
input .name(expr))port.upper_half) to the underlying expression at type-check timeTest plan
regression/verilog/interface/modport_expression1.descchanged from KNOWNBUG to CORE and passesmake -C regression/verilog test)make -C regression/ebmc test)make -C regression/smv test)