[rascani]

Refactor convolution, depthwise convolution, transpose convolution, average
pooling, and max pooling behind shared internal implementations that accept a
private activation-layout mode.

Existing registered operators continue selecting the legacy NCHW-logical
contract over channels-last storage. This commit changes no public schema and no
AOT lowering; it provides the common implementation the following fixed-NHWC
wrappers use.

Local Corstone-300 run of the full Cortex-M suite, including the default-mode
dialect tests and MobileNetV3 lowering, and lintrunner.

Authored with Codex.

[rascani]

Stack from ghstack (oldest at bottom):

• Cortex-M: keep NHWC channel broadcasts quantized #21968
• Cortex-M: add opt-in explicit layout lowering #21967
• Cortex-M: make quantized add and multiply layout-agnostic #21966
• Cortex-M: add a contiguous-layout pad operator #22028
• Cortex-M: add explicit-NHWC runtime operators #21965
• -> Cortex-M: share layout-aware CMSIS-NN kernels #21964
• Channels last: add the common layout pipeline #21963
• Channels last: optimize structural layout regions #21962

[pytorch-bot]

🔗 Helpful Links

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❌ 4 Cancelled Jobs, 1 Unrelated Failure

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• pull / test-qnn-python-imports-linux / linux-job (gh)
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• Test ARM Backend / test-arm / test-backend-linux (arm_tosa_fp, operators) / linux-job (gh)
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• Test ARM Backend / test-arm-vgf / test-backend-linux (arm_vgf_fp, operators) / linux-job (gh)
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FLAKY - The following job failed but was likely due to flakiness present on trunk:

• pull / test-arm-backend-no-driver (test_pytest_models_tosa) / linux-job (gh) (detected as infra flaky with no log or failing log classifier)

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