Cortex-M: share layout-aware CMSIS-NN kernels

[rascani]

Refactor convolution, depthwise convolution, transpose convolution, average
pooling, and max pooling behind shared internal implementations that accept a
private activation-layout mode.

Existing registered operators continue selecting the legacy NCHW-logical
contract over channels-last storage. This commit changes no public schema and no
AOT lowering; it provides the common implementation the following fixed-NHWC
wrappers use.

Local Corstone-300 run of the full Cortex-M suite, including the default-mode
dialect tests and MobileNetV3 lowering, and lintrunner.

Authored with Codex.

[rascani]

Stack from ghstack (oldest at bottom):

• Cortex-M: add an opt-in NHWC method I/O contract #22029
• Cortex-M: keep NHWC channel broadcasts quantized #21968
• Cortex-M: add opt-in explicit layout lowering #21967
• Cortex-M: make quantized add and multiply layout-agnostic #21966
• Cortex-M: add a contiguous-layout pad operator #22028
• Cortex-M: add explicit-NHWC runtime operators #21965
• -> Cortex-M: share layout-aware CMSIS-NN kernels #21964
• Channels last: add the common layout pipeline #21963
• Channels last: absorb boundary layout copies into the method contract #22034
• Channels last: optimize structural layout regions #21962
• Channels last: teach the data-movement passes both permute dialects #22003

[pytorch-bot]

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