docs: add ExternalSystemVerilogModule example to user guide #568 - #703
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AzazelSensei wants to merge 1 commit into
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docs: add ExternalSystemVerilogModule example to user guide #568#703AzazelSensei wants to merge 1 commit into
AzazelSensei wants to merge 1 commit into
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Add a wrapper example, generated instantiation, and notes on definitionName, parameters, and ports. Relates to intel#568.
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Description & Motivation
The external modules user guide page had no example. I added a small wrapper around an existing SystemVerilog module, the generated instantiation, and notes on
definitionName, parameters, and ports.Related Issue(s)
Fixes #568
Testing
Docs-only. The Dart snippet matches the existing
test/external_test.dartwrapper (MyExternalModule/TopModule) and the generated instantiation that test already checks.Backwards-compatibility
No code change.
Documentation
This PR is the documentation update (
doc/user_guide/_docs/A17-external-modules.md).