Module services api_02

.github/configs/mlc_config.json

@@ -19,7 +19,10 @@
       "pattern":"^https://docs.cocotb.org/en/stable/$"
     },
     {
-      "pattern":"^https://www.nandland.com"
+      "pattern": "^https://code\\.visualstudio\\.com/"
+    },
+    {
+      "pattern": "^https://www.nandland.com"
     },
     {
       "pattern":"^https://.*\\.fandom\\.com"

.github/workflows/build_devtool.yml

@@ -22,7 +22,7 @@ jobs:
           uses: flutter-actions/setup-flutter@v2
           with:
             channel: stable
-            version: 3.44.0
+            version: 3.47.2
 
         - name: Run Flutter Test
           run: tool/gh_actions/devtool/run_devtool_test.sh

.github/workflows/general.yml

@@ -215,7 +215,7 @@ jobs:
         uses: flutter-actions/setup-flutter@v2
         with:
           channel: stable
-          version: 3.44.0
+          version: 3.47.2
 
       - name: Run Flutter Test
         run: tool/gh_actions/devtool/run_devtool_test.sh

CHANGELOG.md

@@ -13,6 +13,24 @@
 - Improved generated SystemVerilog to inline packed `Logic.assignSubset` connections into submodule inputs (<https://github.com/intel/rohd/pull/711>).
 - Fixed a bug where isolated bit drivers could be lost beside collapsed ranges (<https://github.com/intel/rohd/pull/711>).
 
+- Added the `ModuleService` API for module-scoped generation, capture, and
+  inspection services. `ModuleServices` registers and looks up services for a
+  built module hierarchy, and `hierarchyJson` exposes its hierarchy as JSON.
+- Added `ArtifactProducingService` and `ModuleServiceArtifact` for
+  transport-neutral output. Artifact-producing services default
+  `outputDirectory` to the current directory and `outputBaseName` to the
+  module definition name, and expose named, media-typed byte streams without
+  requiring filesystem output.
+- Added `SystemVerilogService` for configured SystemVerilog synthesis,
+  in-memory source output, artifact inspection, and explicit directory writes.
+  Added `WaveformService` for in-memory waveform capture with optional file
+  writing through `writeToFile`.
+- Added legacy-compatible `Module.dumpSystemVerilog` and `Module.dumpWaves`
+  convenience methods. `dumpSystemVerilog()` returns simple in-memory output;
+  `dumpWaves()` provides standard VCD capture as the replacement for
+  `WaveDumper`. `WaveDumper` and `generateSynth` are deprecated in favor of
+  these `Module` methods.
+
 ## 0.6.10
 
 - Improved `Logic.replicate(1)` and same-width `signExtend` to return the original signal, eliminating redundant replication modules and generated SystemVerilog (<https://github.com/intel/rohd/pull/689>).

CONTRIBUTING.md

@@ -6,7 +6,7 @@ Anyone interested in participating in ROHD is more than welcome to help!
 
 ## Code of Conduct
 
-ROHD adopts the [Contributor Covenant](https://www.contributor-covenant.org/) v2.1 for the code of conduct. It can be accessed [here](CODE_OF_CONDUCT.md).
+ROHD adopts the [Contributor Covenant](https://www.contributor-covenant.org/) v2.1 for the  [Code of Conduct](CODE_OF_CONDUCT.md).
 
 ## Getting Help
 
@@ -126,7 +126,7 @@ Please include the SPDX tag near the top of any new files you create:
 Here is an example of a recommended file header template:
 
 ```dart
-// Copyright (C) 2021-2023 Intel Corporation
+// Copyright (C) 2021-2026 Intel Corporation
 // SPDX-License-Identifier: BSD-3-Clause
 //
 // example.dart

benchmark/many_submodules_benchmark.dart

@@ -1,4 +1,4 @@
-// Copyright (C) 2024 Intel Corporation
+// Copyright (C) 2024-2026 Intel Corporation
 // SPDX-License-Identifier: BSD-3-Clause
 //
 // many_submodules_benchmark.dart
@@ -33,7 +33,7 @@ class ManySubmodulesBenchmark extends AsyncBenchmarkBase {
   Future<void> run() async {
     final dut = ManySubmodulesModule(Logic(), numSubModules: 10000);
     await dut.build();
-    dut.generateSynth();
+    dut.dumpSystemVerilog();
   }
 }
 

benchmark/wave_dump_benchmark.dart

@@ -1,4 +1,4 @@
-// Copyright (C) 2023 Intel Corporation
+// Copyright (C) 2023-2026 Intel Corporation
 // SPDX-License-Identifier: BSD-3-Clause
 //
 // wave_dump_benchmark.dart
@@ -56,7 +56,7 @@ class WaveDumpBenchmark extends AsyncBenchmarkBase {
     _mod = _ModuleToDump(Logic(), _clk);
     await _mod.build();
 
-    WaveDumper(_mod, outputPath: _vcdTemporaryPath);
+    _mod.dumpWaves(outputPath: _vcdTemporaryPath);
 
     await Simulator.run();
 

doc/tutorials/chapter_1/01_setup_installation.md

@@ -162,7 +162,7 @@ Future<void> main({bool noPrint = false}) async {
 
   // Let's see what this module looks like as SystemVerilog, so we can pass it
   // to other tools.
-  final systemVerilogCode = counter.generateSynth();
+  final systemVerilogCode = counter.dumpSystemVerilog();
   if (!noPrint) {
     print(systemVerilogCode);
   }
@@ -175,7 +175,7 @@ Future<void> main({bool noPrint = false}) async {
 
   // Attach a waveform dumper so we can see what happens.
   if (!noPrint) {
-    WaveDumper(counter);
+    counter.dumpWaves();
   }
 
   // Drop reset at time 25.

doc/tutorials/chapter_2/helper.dart

@@ -13,7 +13,8 @@ import 'package:rohd/rohd.dart';
 
 Future<void> displaySystemVerilog(Module mod) async {
   await mod.build();
-  print('\nYour System Verilog Equivalent Code: \n ${mod.generateSynth()}');
+  print('\nYour System Verilog Equivalent Code: \n '
+      '${mod.dumpSystemVerilog()}');
 }
 
 class LogicInitialization extends Module {

doc/tutorials/chapter_3/answers/exercise_sv.dart

@@ -1,3 +1,12 @@
+// Copyright (C) 2023-2026 Intel Corporation
+// SPDX-License-Identifier: BSD-3-Clause
+//
+// exercise_sv.dart
+// Chapter 3 SystemVerilog exercise answer.
+//
+// 2023 March 30
+// Author: Yao Jing Quek <yao.jing.quek@intel.com>
+
 import 'package:rohd/rohd.dart';
 import 'package:test/test.dart';
 import 'helper.dart';
@@ -33,7 +42,7 @@ void main() async {
   await fSub.build();
 
   // ignore: avoid_print - tutorial
-  print(fSub.generateSynth());
+  print(fSub.dumpSystemVerilog());
 
   test('should return 0 when a and b equal 1', () {
     a.put(1);

doc/tutorials/chapter_3/full_adder.dart

@@ -1,3 +1,12 @@
+// Copyright (C) 2023-2026 Intel Corporation
+// SPDX-License-Identifier: BSD-3-Clause
+//
+// full_adder.dart
+// Chapter 3 full-adder tutorial example.
+//
+// 2023 March 3
+// Author: Yao Jing Quek <yao.jing.quek@intel.com>
+
 // ignore_for_file: avoid_print - tutorial
 
 import 'package:rohd/rohd.dart';
@@ -76,5 +85,5 @@ void main() async {
   final mod = FullAdderModule(a, b, cIn, faOps);
   await mod.build();
 
-  print(mod.generateSynth());
+  print(mod.dumpSystemVerilog());
 }

doc/tutorials/chapter_4/answers/exercise_1_sv.dart

@@ -1,3 +1,12 @@
+// Copyright (C) 2023-2026 Intel Corporation
+// SPDX-License-Identifier: BSD-3-Clause
+//
+// exercise_1_sv.dart
+// Chapter 4 SystemVerilog exercise answer.
+//
+// 2023 April 11
+// Author: Yao Jing Quek <yao.jing.quek@intel.com>
+
 import 'package:rohd/rohd.dart';
 import 'package:test/test.dart';
 
@@ -10,7 +19,7 @@ void main() async {
   final mod = NBitAdder(a, b);
   await mod.build();
 
-  print(mod.generateSynth());
+  print(mod.dumpSystemVerilog());
 
   test('should return 255 when both inputs are added', () {
     a.put(127);

doc/tutorials/chapter_4/answers/exercise_2_sv.dart

@@ -1,3 +1,12 @@
+// Copyright (C) 2023-2026 Intel Corporation
+// SPDX-License-Identifier: BSD-3-Clause
+//
+// exercise_2_sv.dart
+// Chapter 4 SystemVerilog exercise answer.
+//
+// 2023 April 11
+// Author: Yao Jing Quek <yao.jing.quek@intel.com>
+
 import 'package:rohd/rohd.dart';
 import 'package:test/test.dart';
 
@@ -9,7 +18,7 @@ void main() async {
 
   final mod = NBitSubtractor(a, b);
   await mod.build();
-  print(mod.generateSynth());
+  print(mod.dumpSystemVerilog());
 
   test('should return 5 when a is 25 and b is 20', () {
     a.put(25);

doc/tutorials/chapter_4/basic_generation_sv.dart

@@ -1,3 +1,12 @@
+// Copyright (C) 2023-2026 Intel Corporation
+// SPDX-License-Identifier: BSD-3-Clause
+//
+// basic_generation_sv.dart
+// Chapter 4 basic SystemVerilog generation tutorial example.
+//
+// 2023 April 11
+// Author: Yao Jing Quek <yao.jing.quek@intel.com>
+
 import 'package:rohd/rohd.dart';
 import 'package:test/test.dart';
 
@@ -78,7 +87,7 @@ void main() async {
 
   await nbitAdder.build();
 
-  print(nbitAdder.generateSynth());
+  print(nbitAdder.dumpSystemVerilog());
 
   test('should return 10 when both inputs are 5.', () {
     a.put(5);

doc/tutorials/chapter_5/00_basic_modules.md

@@ -95,7 +95,7 @@ Do note that the `build()` method returns a `Future<void>`, not just `void`. Thi
 
 ## Converting ROHD Module to System Verilog RTL
 
-Next, we can see how extending your `Logic` to `Module` enables the generation of system Verilog code. Building on the previous example, we've made some slight modifications by adding `simModule.build()` and `simModule.generateSynth()`.
+Next, we can see how extending your `Logic` to `Module` enables the generation of system Verilog code. Building on the previous example, we've made some slight modifications by adding `simModule.build()` and `simModule.dumpSystemVerilog()`.
 
 ```dart
 void main() async {
@@ -106,15 +106,16 @@ void main() async {
     await simModule.build();
 
     // Print out system verilog code
-    print(simModule.generateSynth());
+    print(simModule.dumpSystemVerilog());
 
     test('should return input value.',
           () => expect(simModule.out.value.toInt(), equals(1)));
 
     // Add this to test on generate system verilog code
     test(
           'should generate system verilog code.',
-        () => expect(simModule.generateSynth(), contains('module SimpleModule(')));
+        () => expect(simModule.dumpSystemVerilog(),
+          contains('module SimpleModule(')));
 }
 ```
 

doc/tutorials/chapter_5/answers/full_adder.dart

@@ -1,3 +1,12 @@
+// Copyright (C) 2023-2026 Intel Corporation
+// SPDX-License-Identifier: BSD-3-Clause
+//
+// full_adder.dart
+// Chapter 5 full-adder exercise answer.
+//
+// 2023 May 26
+// Author: Yao Jing Quek <yao.jing.quek@intel.com>
+
 // ignore_for_file: avoid_print - tutorial
 
 import 'package:rohd/rohd.dart';
@@ -49,7 +58,7 @@ void main() async {
   final mod = FullAdder(a: a, b: b, carryIn: cIn);
   await mod.build();
 
-  print(mod.generateSynth());
+  print(mod.dumpSystemVerilog());
 
   test('should return true if result sum similar to truth table.', () {
     for (var i = 0; i <= 1; i++) {

doc/tutorials/chapter_5/answers/full_subtractor.dart

@@ -1,3 +1,12 @@
+// Copyright (C) 2023-2026 Intel Corporation
+// SPDX-License-Identifier: BSD-3-Clause
+//
+// full_subtractor.dart
+// Chapter 5 full-subtractor exercise answer.
+//
+// 2023 May 26
+// Author: Yao Jing Quek <yao.jing.quek@intel.com>
+
 // ignore_for_file: avoid_print - tutorial
 
 import 'package:rohd/rohd.dart';
@@ -44,7 +53,7 @@ Future<void> main() async {
 
   await diff.build();
 
-  print(diff.generateSynth());
+  print(diff.dumpSystemVerilog());
 
   test('should return true if results matched truth table', () {
     for (var i = 0; i <= 1; i++) {

doc/tutorials/chapter_5/answers/n_bit_subtractor.dart

@@ -1,3 +1,12 @@
+// Copyright (C) 2023-2026 Intel Corporation
+// SPDX-License-Identifier: BSD-3-Clause
+//
+// n_bit_subtractor.dart
+// Chapter 5 N-bit subtractor exercise answer.
+//
+// 2023 May 26
+// Author: Yao Jing Quek <yao.jing.quek@intel.com>
+
 // ignore_for_file: avoid_print - tutorial
 
 import 'package:rohd/rohd.dart';
@@ -36,7 +45,7 @@ Future<void> main() async {
   final mod = NBitFullSubtractor(a, b);
   await mod.build();
 
-  print(mod.generateSynth());
+  print(mod.dumpSystemVerilog());
 
   test('should return 1 when a is 8 and b is 7.', () {
     a.put(8);

doc/tutorials/chapter_5/n_bit_adder.dart

@@ -1,3 +1,12 @@
+// Copyright (C) 2023-2026 Intel Corporation
+// SPDX-License-Identifier: BSD-3-Clause
+//
+// n_bit_adder.dart
+// Chapter 5 N-bit adder tutorial example.
+//
+// 2023 April 11
+// Author: Yao Jing Quek <yao.jing.quek@intel.com>
+
 import 'package:rohd/rohd.dart';
 import 'package:test/test.dart';
 
@@ -79,7 +88,7 @@ void main() async {
 
   await nbitAdder.build();
 
-  // print(nbitAdder.generateSynth());
+  // print(nbitAdder.dumpSystemVerilog());
 
   test('should return 20 when A and B perform add.', () {
     a.put(15);