arch/arm/gd21f4: Gd32f470vit6 port

arch/arm/Kconfig

@@ -160,6 +160,7 @@ config ARCH_CHIP_GD32F4
 	select ARCH_HAVE_I2CRESET
 	select ARCH_HAVE_HEAPCHECK
 	select ARCH_HAVE_PROGMEM
+	select ARCH_HAVE_RAMFUNCS
 	select ARCH_HAVE_SPI_BITORDER
 	select ARCH_HAVE_TICKLESS
 	select ARM_HAVE_MPU_UNIFIED

arch/arm/src/gd32f4/CMakeLists.txt

@@ -66,4 +66,8 @@ if(CONFIG_GD32F4_SDIO)
   list(APPEND SRCS gd32f4xx_sdio.c)
 endif()
 
+if(CONFIG_GD32F4_CAN)
+  list(APPEND SRCS gd32f4xx_can.c)
+endif()
+
 target_sources(arch PRIVATE ${SRCS})

arch/arm/src/gd32f4/Kconfig

@@ -192,6 +192,155 @@ config GD32F4_DFU
 		Configure and position code for use with the GD MCU DFU bootloader.  Do
 		not select this option if you will load code using JTAG/SWM.
 
+config GD32F4_HAVE_OTA_PARTITION
+	bool
+	default n
+
+choice
+	prompt "Application Image Format"
+	depends on ARCH_CHIP_GD32F4
+	default GD32F4_APP_FORMAT_LEGACY
+
+config GD32F4_APP_FORMAT_LEGACY
+	bool "Legacy format"
+
+config GD32F4_APP_FORMAT_MCUBOOT
+	bool "MCUboot-bootable format"
+	select GD32F4_HAVE_OTA_PARTITION
+	depends on EXPERIMENTAL
+
+endchoice # Application Image Format
+
+if GD32F4_HAVE_OTA_PARTITION
+
+config GD32F4_MCUBOOT_HEADER_SIZE
+	hex "MCUboot image header size"
+	default 0x200
+	depends on GD32F4_APP_FORMAT_MCUBOOT
+
+menuconfig GD32F4_PROGMEM_OTA_PARTITION
+	bool "MTD driver for OTA partition"
+	default n
+	depends on GD32F4_APP_FORMAT_MCUBOOT
+	select BCH
+	select MTD
+	select MTD_BYTE_WRITE
+	select MTD_PARTITION
+	select MTD_PROGMEM
+	select GD32F4_PROGMEM
+
+if GD32F4_PROGMEM_OTA_PARTITION
+
+# EnergyOS 2 MiB Layout v2 (Code 512K + Data 1536K @ 0x08080000):
+#   loader 128K | code-reserve 384K (factory/security/sys/user/ota-state) |
+#   primary 768K @0x80000 | secondary 768K @0x140000 (no scratch; OVERWRITE)
+
+config GD32F4_OTA_BOOT_DEVPATH
+	string "Bootloader (loader) device path"
+	default "/dev/otaboot"
+
+config GD32F4_OTA_PRIMARY_SLOT_DEVPATH
+	string "Primary slot device path"
+	default "/dev/ota0"
+
+config GD32F4_OTA_SECONDARY_SLOT_DEVPATH
+	string "Secondary slot device path"
+	default "/dev/ota1"
+
+config GD32F4_OTA_SCRATCH_DEVPATH
+	string "Scratch partition device path (unused in OVERWRITE)"
+	default "/dev/otascratch"
+
+config GD32F4_OTA_FACTORY_DEVPATH
+	string "Factory data device path"
+	default "/dev/factory"
+
+config GD32F4_OTA_SECURITY_DEVPATH
+	string "Security data device path"
+	default "/dev/security"
+
+config GD32F4_OTA_SYSCONFIG_DEVPATH
+	string "System config device path"
+	default "/dev/sysconfig"
+
+config GD32F4_OTA_USERCONFIG_DEVPATH
+	string "User config device path"
+	default "/dev/userconfig"
+
+config GD32F4_OTA_STATE_DEVPATH
+	string "OTA / boot state device path"
+	default "/dev/ota-state"
+
+config GD32F4_OTA_BOOT_OFFSET
+	hex "Bootloader (loader) offset"
+	default 0x0
+
+config GD32F4_OTA_PRIMARY_SLOT_OFFSET
+	hex "Primary slot offset"
+	default 0x80000
+
+config GD32F4_OTA_SECONDARY_SLOT_OFFSET
+	hex "Secondary slot offset"
+	default 0x140000
+
+config GD32F4_OTA_SCRATCH_OFFSET
+	hex "Scratch partition offset (unused when size 0)"
+	default 0x0
+
+config GD32F4_OTA_FACTORY_OFFSET
+	hex "Factory data offset (in code-reserve)"
+	default 0x20000
+
+config GD32F4_OTA_SECURITY_OFFSET
+	hex "Security data offset"
+	default 0x28000
+
+config GD32F4_OTA_SYSCONFIG_OFFSET
+	hex "System config offset"
+	default 0x38000
+
+config GD32F4_OTA_USERCONFIG_OFFSET
+	hex "User config offset"
+	default 0x48000
+
+config GD32F4_OTA_STATE_OFFSET
+	hex "OTA / boot state offset"
+	default 0x58000
+
+config GD32F4_OTA_BOOT_SIZE
+	hex "Bootloader (loader) size (in bytes)"
+	default 0x20000
+
+config GD32F4_OTA_SLOT_SIZE
+	hex "Application image slot size (in bytes)"
+	default 0xc0000
+
+config GD32F4_OTA_SCRATCH_SIZE
+	hex "Scratch partition size (in bytes; 0 = disabled)"
+	default 0x0
+
+config GD32F4_OTA_FACTORY_SIZE
+	hex "Factory data size (in bytes)"
+	default 0x8000
+
+config GD32F4_OTA_SECURITY_SIZE
+	hex "Security data size (in bytes)"
+	default 0x10000
+
+config GD32F4_OTA_SYSCONFIG_SIZE
+	hex "System config size (in bytes)"
+	default 0x10000
+
+config GD32F4_OTA_USERCONFIG_SIZE
+	hex "User config size (in bytes)"
+	default 0x10000
+
+config GD32F4_OTA_STATE_SIZE
+	hex "OTA / boot state size (in bytes)"
+	default 0x8000
+
+endif # GD32F4_PROGMEM_OTA_PARTITION
+endif # GD32F4_HAVE_OTA_PARTITION
 
 menu "GD32 Peripheral Support"
 
@@ -270,12 +419,14 @@ config GD32F4_BKPSRAM
 config GD32F4_CAN0
 	bool "CAN0"
 	select CAN
+	select ARCH_HAVE_CAN_ERRORS
 	select GD32F4_CAN
 	default n
 
 config GD32F4_CAN1
 	bool "CAN1"
 	select CAN
+	select ARCH_HAVE_CAN_ERRORS
 	select GD32F4_CAN
 	default n
 
@@ -323,6 +474,7 @@ config GD32F4_ENETMAC
 	depends on GD32F4_HAVE_ENETMAC
 	select NETDEVICES
 	select ARCH_HAVE_PHY
+	select ARCH_HAVE_NETDEV_STATISTICS
 
 config GD32F4_EXMC
 	bool "EXMC"
@@ -344,6 +496,23 @@ config GD32F4_PROGMEM
 		Use a part of GD32F4xx's internal flash memory as a
 		Memory-Technology-Device (MTD).
 
+config GD32F4_FLASH_HAL_SELFTEST
+	bool "GD32 Flash HAL self-test before MCUboot boot_go"
+	default n
+	depends on GD32F4_PROGMEM && GD32F4_GD32F470
+	---help---
+		Run Secondary→SRAM→Primary Flash HAL matrix (R1/E1/W1/C1/C2/L1)
+		before boot_go. Intended for OVERWRITE bring-up only; disable for
+		production loader. Results are printed via syslog after FMC idle.
+
+config GD32F4_FLASH_HAL_SELFTEST_FULL
+	bool "Include full-slot Secondary→Primary copy (C3)"
+	default n
+	depends on GD32F4_FLASH_HAL_SELFTEST
+	---help---
+		Also copy the entire 768 KiB slot (C3). Destroys Primary contents;
+		Secondary must hold a valid image.
+
 config GD32F4_MTD
 	bool "MTD driver"
 	default n
@@ -1820,7 +1989,7 @@ config USART5_RS485_DIR_POLARITY
 	int "Configure USART5 RS-485 DIR pin polarity"
 	default 1
 	range 0 1
-	depends on USART1_RS485
+	depends on USART5_RS485
 	---help---
 		Polarity of GPIO_USART5_RS485_DIR pin for RS-485 on USART5.
 		The state on DIR pin: 0 - receive , 1 - transmit.
@@ -2363,6 +2532,18 @@ config GD32F4_PHY_INIT
 		provide the function of phyinitialize();  Before first uses the PHY, the GD32F4 Ethernet
 		driver will call this function one time .
 
+config GD32F4_PHY_SWITCH
+	bool "Ethernet PHY is an unmanaged switch (e.g. KSZ8863)"
+	default n
+	depends on GD32F4_PHY_INIT
+	---help---
+		Select when the RMII MAC attaches to a switch MAC port (e.g. KSZ8863
+		Port3), not a copper PHY. Board logic hard-resets the switch; Port1/2
+		copper keep strap autoneg. Skip MIIM soft-reset and MCR force at
+		GD32F4_PHY_ADDR (those target copper Port1 and can disable AN). MAC
+		speed/duplex still follow GD32F4_ENET_MODE_* / SPEEDMODE_* when
+		autoneg is disabled.
+
 config GD32F4_MII
 	bool "Use the media-independent interface (MII) interface"
 	default n
@@ -2582,6 +2763,44 @@ config GD32F4_USB_ITRMP
 menu "CAN driver configuration"
 	depends on GD32F4_CAN
 
+config GD32F4_CAN0_BAUD
+	int "CAN0 BAUD"
+	depends on GD32F4_CAN0
+	default 500000
+	---help---
+		CAN0 BAUD rate.  Required if CONFIG_GD32F4_CAN0 is defined.
+		Default 500000 for Board1 Power CAN MVP.
+
+config GD32F4_CAN1_BAUD
+	int "CAN1 BAUD"
+	depends on GD32F4_CAN1
+	default 500000
+	---help---
+		CAN1 BAUD rate.  Required if CONFIG_GD32F4_CAN1 is defined.
+
+config GD32F4_CAN_TSEG1
+	int "TSEG1 quanta"
+	default 6
+	---help---
+		The number of CAN time quanta in segment 1. Default: 6
+		(bit time = TSEG1 + TSEG2 + 1 = 14 quanta with default TSEG2).
+
+config GD32F4_CAN_TSEG2
+	int "TSEG2 quanta"
+	default 7
+	---help---
+		The number of CAN time quanta in segment 2. Default: 7
+
+config GD32F4_CAN_REGDEBUG
+	bool "CAN Register level debug"
+	depends on DEBUG_CAN_INFO
+	default n
+	---help---
+		Output detailed register-level CAN device debug information.
+		Requires also CONFIG_DEBUG_CAN_INFO.
+
+comment "Loopback mode uses Device Drivers -> CAN Driver Support -> CONFIG_CAN_LOOPBACK"
+
 endmenu # "CAN driver configuration"
 
 

arch/arm/src/gd32f4/Make.defs

@@ -64,3 +64,7 @@ endif
 ifeq ($(CONFIG_GD32F4_SDIO),y)
 CHIP_CSRCS += gd32f4xx_sdio.c
 endif
+
+ifeq ($(CONFIG_GD32F4_CAN),y)
+CHIP_CSRCS += gd32f4xx_can.c
+endif

arch/arm/src/gd32f4/gd32f4xx.h

@@ -50,5 +50,6 @@
 #include "gd32f4xx_i2c.h"
 #include "gd32f4xx_syscfg.h"
 #include "gd32f4xx_sdio.h"
+#include "gd32f4xx_can.h"
 
 #endif /* __ARCH_ARM_SRC_GD32F4_GD32F4XX_H */

arch/arm/src/gd32f4/gd32f4xx_allocateheap.c

@@ -84,9 +84,18 @@
 
 #if defined(CONFIG_GD32F4_GD32F4XX)
 
-/* Set the end of system SRAM */
+/* Set the end of system SRAM.
+ *
+ * GD32F470 has up to 512KB contiguous System SRAM (0x20000000..).
+ * Older NuttX defaults only covered the smaller F4xx window
+ * (SRAM_END=0x20020000 → ~40KB heap after BSS), which OOMs when
+ * Board1 bringup starts webui + pylon_bms + sim_sdk + sim_pcs.
+ * Prefer CONFIG_RAM_END from the board defconfig.
+ */
 
-#  if defined(CONFIG_GD32F4_GD32F450)
+#  if defined(CONFIG_GD32F4_GD32F470)
+#    define SRAM_END CONFIG_RAM_END
+#  elif defined(CONFIG_GD32F4_GD32F450)
 #    if defined(CONFIG_GD32F4_GD32F450XI)
 #      define SRAM_END 0x20070000
 #    else