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Validation#39

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Preston-Walker wants to merge 4 commits into
Xilinx:mainfrom
Preston-Walker:validation
Open

Validation#39
Preston-Walker wants to merge 4 commits into
Xilinx:mainfrom
Preston-Walker:validation

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@Preston-Walker

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Phase 1: widen cell-count decrease threshold from 3% to 50% in the structural
checker to avoid false negatives when Vivado optimization passes legitimately
reduce cell count.

Phase 2 simulation overhaul:

  • Replace the dead "paired" testbench mode with a trace-replay architecture:
    golden design writes stimulus+outputs to a .hex trace; revised design replays
    the same stimulus and outputs are compared. Removes the paired testbench
    template entirely.
  • Add a content-addressed xelab snapshot cache (keyed on SHA-256 of the golden
    DCP + validator script) so repeated validation runs skip slow elaboration.
    Cache directory excluded via .gitignore.
  • Replace hardcoded LFSR seed (0xDEADBEEF) with a per-run random seed drawn
    from os.urandom(4). Seed is passed to xsim at runtime via +LFSR_SEED so
    xelab snapshots remain seed-independent and the cache continues to work.
    Seed is encoded in the cached trace filename (seed_XXXXXXXX_vectors_N.hex)
    so a cache hit naturally reuses the same seed.
  • Add --seed CLI flag for reproducible/deterministic runs during development.
  • LFSR_SEED testplusarg is now only passed for golden trace generation, not
    revised replay (which has no LFSR and ignored it).

Preston-Walker and others added 2 commits July 7, 2026 09:01
…e, remove dead testbench mode

Co-authored-by: Cursor <cursoragent@cursor.com>
Co-authored-by: Cursor <cursoragent@cursor.com>
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