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Optimize tail-padding reuse [NFC] - #9084

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kripken wants to merge 4 commits into
WebAssembly:mainfrom
kripken:smalll
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Optimize tail-padding reuse [NFC]#9084
kripken wants to merge 4 commits into
WebAssembly:mainfrom
kripken:smalll

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@kripken

@kripken kripken commented Sep 8, 2026

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One some ABIs, if a base class ends with padding, derived classes right after it
can reuse that padding, placing their data there. This PR optimizes the key
Expression class that way.

Size changes on linux64 (common classes):

class old size new size
LocalGet 24 16
LocalSet 32 24
Load 64 48
Store 80 64
Unary 32 24
Binary 40 32
StructGet 40 24
StructSet 48 32

On 5 real-world binaries I tested, this reduced peak RAM usage by
3%, 4%, 6%, 9%, 9%.

@kripken
kripken requested a review from a team as a code owner September 8, 2026 23:48
@kripken
kripken requested review from aheejin and removed request for a team September 8, 2026 23:48

@aheejin aheejin left a comment

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Nice idea!

Gemini suggested we can make these further improvements. I haven't checked them by myself though. (Also not necessarily in this PR)

  1. Call: Move bool isReturn to the top (64 -> 56 bytes)
  2. CallIndirect: Move bool isReturn to the top (80 -> 72 bytes)
  3. CallRef: Move bool isReturn to the top (64 -> 56 bytes)
  4. I31Get: Move bool signed_ to the top (32 -> 24 bytes)
  5. AtomicRMW: Move MemoryOrder order to the top (64 -> 56 bytes)
  6. AtomicCmpxchg: Move MemoryOrder order to the top (64 -> 56 bytes)
  7. StructRMW: Move MemoryOrder order to the top (48 -> 40 bytes)
  8. StructCmpxchg: Move MemoryOrder order to the top (48 -> 40 bytes)
  9. ArrayRMW: Move MemoryOrder order to the top (48 -> 40 bytes)
  10. ArrayCmpxchg: Move MemoryOrder order to the top (56 -> 48 bytes)
  11. SIMDReplace: Move uint8_t index to the top (40 -> 32 bytes)

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2 participants