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1 | 1 | // SPDX-License-Identifier: MIT OR Apache-2.0 |
2 | 2 | // |
3 | 3 | // Copyright (c) 2018-2023 Andre Richter <andre.o.richter@gmail.com> |
| 4 | +// Copyright (c) 2026 Devansh Lodha <devanshlodha12@gmail.com> |
4 | 5 |
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5 | 6 | //! BSP Memory Management. |
6 | 7 | //! |
@@ -147,6 +148,45 @@ pub(super) mod map { |
147 | 148 | pub const END: Address<Physical> = Address::new(0xFF85_0000); |
148 | 149 | } |
149 | 150 |
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| 151 | + /// Physical devices. |
| 152 | + #[cfg(feature = "bsp_rpi5")] |
| 153 | + pub mod mmio { |
| 154 | + use super::*; |
| 155 | + |
| 156 | + // GICv2 on BCM2712 (Northbridge) |
| 157 | + pub const GICD_START: Address<Physical> = Address::new(0x10_7FFF_9000); |
| 158 | + pub const GICD_SIZE: usize = 0x1000; |
| 159 | + pub const GICC_START: Address<Physical> = Address::new(0x10_7FFF_A000); |
| 160 | + pub const GICC_SIZE: usize = 0x1000; |
| 161 | + |
| 162 | + // MIP (Machine Interrupt Peripheral) |
| 163 | + pub const MIP_START: Address<Physical> = Address::new(0x10_0013_0000); |
| 164 | + pub const MIP_SIZE: usize = 0x1000; |
| 165 | + |
| 166 | + // PCIe Root Complex |
| 167 | + pub const PCIE_RC_START: Address<Physical> = Address::new(0x10_0012_0000); |
| 168 | + pub const PCIE_RC_SIZE: usize = 0x1000; |
| 169 | + |
| 170 | + // RP1 Southbridge Config Space (ECAM) |
| 171 | + // 0x1F_0010_0000 -> 0x1F_0050_0000 (4MB) covers Config Space + MSI-X Table |
| 172 | + pub const RP1_CFG_START: Address<Physical> = Address::new(0x1F_0010_0000); |
| 173 | + pub const RP1_CFG_SIZE: usize = 0x40_0000; |
| 174 | + |
| 175 | + // RP1 Peripherals |
| 176 | + // UART is at offset 0x30000 in the RP1 peripheral bar |
| 177 | + pub const PL011_UART_START: Address<Physical> = Address::new(0x1F_0003_0000); |
| 178 | + pub const PL011_UART_SIZE: usize = 0x1000; |
| 179 | + |
| 180 | + pub const GPIO_START: Address<Physical> = Address::new(0x1F_000D_0000); |
| 181 | + pub const GPIO_SIZE: usize = 0x1000; |
| 182 | + |
| 183 | + pub const PADS_START: Address<Physical> = Address::new(0x1F_000F_0000); |
| 184 | + pub const PADS_SIZE: usize = 0x1000; |
| 185 | + |
| 186 | + // Used by Translation Table Tool |
| 187 | + pub const END: Address<Physical> = Address::new(0x20_0000_0000); |
| 188 | + } |
| 189 | + |
150 | 190 | pub const END: Address<Physical> = mmio::END; |
151 | 191 | } |
152 | 192 |
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