From eb15032e6a774c790f0bad1aec698761b6f03624 Mon Sep 17 00:00:00 2001 From: James Burton Date: Sat, 19 Sep 2026 21:44:20 +0100 Subject: [PATCH 1/2] JIT: mark vpshufbitqmb as a three-operand AVX instruction VPSHUFBITQMB has the form 'k1 {k2}, xmm2, xmm3/m128' -- a kmask destination plus two source operands. Every other three-operand mask-producing EVEX instruction in instrsxarch.h carries INS_FLAGS_IsDstDstSrcAVXInstruction (vpcmpb, vpcmpub, vpcmpw, vpcmpuw, vptestmb/d/q/w, vptestnmb/d/q/w, vpblendmb); vpshufbitqmb does not. Without the flag IsThreeOperandAVXInstruction returns false, so any attempt to emit the instruction asserts in emitIns_R_R_S (emitxarch.cpp:8572) on a Checked JIT, and would emit a malformed encoding on Release. The row is currently unreachable -- no HARDWARE_INTRINSIC entry maps to INS_vpshufbitqmb -- so no shipping code is affected today. It was found while implementing the BITALG intrinsics for #96162, whose Avx512BitAlg.ShuffleBits would be the first consumer. Fixing it separately so the table is correct independently of that work. Co-Authored-By: Claude Opus 5 (1M context) --- src/coreclr/jit/instrsxarch.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/coreclr/jit/instrsxarch.h b/src/coreclr/jit/instrsxarch.h index fcd6e9b3e06f6b..89b8a2e00a415b 100644 --- a/src/coreclr/jit/instrsxarch.h +++ b/src/coreclr/jit/instrsxarch.h @@ -988,7 +988,7 @@ INST3(vpshrdvd, "vpshrdvd", IUM_WR, BAD_CODE, BAD_ INST3(vpshrdvq, "vpshrdvq", IUM_WR, BAD_CODE, BAD_CODE, SSE38(0x73), ILLEGAL, ILLEGAL, INS_TT_FULL, Input_64Bit | KMask_Base2 | REX_W1 | Encoding_EVEX) // Concatenate and Variable Shift Packed Data Right Logical INST3(vpshrdvw, "vpshrdvw", IUM_WR, BAD_CODE, BAD_CODE, SSE38(0x72), ILLEGAL, ILLEGAL, INS_TT_FULL_MEM, Input_16Bit | KMask_Base8 | REX_W1 | Encoding_EVEX) // Concatenate and Variable Shift Packed Data Right Logical INST3(vpshrdw, "vpshrdw", IUM_WR, BAD_CODE, BAD_CODE, SSE3A(0x72), ILLEGAL, ILLEGAL, INS_TT_FULL_MEM, Input_16Bit | KMask_Base8 | REX_W1 | Encoding_EVEX) // Concatenate and Shift Packed Data Right Logical -INST3(vpshufbitqmb, "vpshufbitqmb", IUM_WR, BAD_CODE, BAD_CODE, SSE38(0x8F), 6C, 1C, INS_TT_FULL_MEM, Input_8Bit | KMask_Base16 | REX_W0 | Encoding_EVEX) // Shuffle Bits From Quadword Elements Using Byte Indexes Into Mask +INST3(vpshufbitqmb, "vpshufbitqmb", IUM_WR, BAD_CODE, BAD_CODE, SSE38(0x8F), 6C, 1C, INS_TT_FULL_MEM, Input_8Bit | KMask_Base16 | REX_W0 | Encoding_EVEX | INS_FLAGS_IsDstDstSrcAVXInstruction) // Shuffle Bits From Quadword Elements Using Byte Indexes Into Mask // Instructions for AVX512-BF16, AVX512-FP16 INST3(vaddph, "vaddph", IUM_WR, BAD_CODE, BAD_CODE, PCKFLTMAP(0x05, 0x58), 4C, 2X, INS_TT_FULL_MEM, Input_16Bit | KMask_Base8 | REX_W0 | Encoding_EVEX) // Add Packed FP16 Values From d143c2d4e0612bed4a26e04278a56f1607e01f95 Mon Sep 17 00:00:00 2001 From: James Burton Date: Sat, 19 Sep 2026 22:44:32 +0100 Subject: [PATCH 2/2] Restore instrsxarch.h column alignment Addresses the Copilot review nit: the added flag had compressed the REX_W0 / Encoding_EVEX columns. Now matches the surrounding rows and vptestmb's formatting exactly (Encoding_EVEX at column 255). Whitespace only; no functional change. Co-Authored-By: Claude Opus 5 (1M context) --- src/coreclr/jit/instrsxarch.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/coreclr/jit/instrsxarch.h b/src/coreclr/jit/instrsxarch.h index 89b8a2e00a415b..84807a7c1c69f6 100644 --- a/src/coreclr/jit/instrsxarch.h +++ b/src/coreclr/jit/instrsxarch.h @@ -988,7 +988,7 @@ INST3(vpshrdvd, "vpshrdvd", IUM_WR, BAD_CODE, BAD_ INST3(vpshrdvq, "vpshrdvq", IUM_WR, BAD_CODE, BAD_CODE, SSE38(0x73), ILLEGAL, ILLEGAL, INS_TT_FULL, Input_64Bit | KMask_Base2 | REX_W1 | Encoding_EVEX) // Concatenate and Variable Shift Packed Data Right Logical INST3(vpshrdvw, "vpshrdvw", IUM_WR, BAD_CODE, BAD_CODE, SSE38(0x72), ILLEGAL, ILLEGAL, INS_TT_FULL_MEM, Input_16Bit | KMask_Base8 | REX_W1 | Encoding_EVEX) // Concatenate and Variable Shift Packed Data Right Logical INST3(vpshrdw, "vpshrdw", IUM_WR, BAD_CODE, BAD_CODE, SSE3A(0x72), ILLEGAL, ILLEGAL, INS_TT_FULL_MEM, Input_16Bit | KMask_Base8 | REX_W1 | Encoding_EVEX) // Concatenate and Shift Packed Data Right Logical -INST3(vpshufbitqmb, "vpshufbitqmb", IUM_WR, BAD_CODE, BAD_CODE, SSE38(0x8F), 6C, 1C, INS_TT_FULL_MEM, Input_8Bit | KMask_Base16 | REX_W0 | Encoding_EVEX | INS_FLAGS_IsDstDstSrcAVXInstruction) // Shuffle Bits From Quadword Elements Using Byte Indexes Into Mask +INST3(vpshufbitqmb, "vpshufbitqmb", IUM_WR, BAD_CODE, BAD_CODE, SSE38(0x8F), 6C, 1C, INS_TT_FULL_MEM, Input_8Bit | KMask_Base16 | REX_W0 | Encoding_EVEX | INS_FLAGS_IsDstDstSrcAVXInstruction) // Shuffle Bits From Quadword Elements Using Byte Indexes Into Mask // Instructions for AVX512-BF16, AVX512-FP16 INST3(vaddph, "vaddph", IUM_WR, BAD_CODE, BAD_CODE, PCKFLTMAP(0x05, 0x58), 4C, 2X, INS_TT_FULL_MEM, Input_16Bit | KMask_Base8 | REX_W0 | Encoding_EVEX) // Add Packed FP16 Values